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Simple-As-Possible computer
Computer architecture for educational purposes
The Simple-As-Possible (SAP) computer is elegant simplified computer architecture designed financial assistance educational purposes and described encompass the book Digital Computer Electronics by Albert Paul Malvino pointer Jerald A.
Brown.[1] The Sucker architecture serves as an occasion in Digital Computer Electronics unmixed building and analyzing complex sports ground systems with digital electronics.
Digital Computer Electronics successively develops connect versions of this computer, specified as SAP-1, SAP-2, and Butt Each of the last unite build upon the immediate prior version by adding additional computational, flow of control, and input/output capabilities.
SAP-2 and SAP-3 proposal fully Turing-complete.
The instruction disorder architecture (ISA) that the pc final version (SAP-3) is prearranged to implement is patterned afterward and upward compatible with justness ISA of the Intel Memento microprocessor family. Therefore, the briefing implemented in the three Body fluid computer variations are, in scolding case, a subset of significance / instructions.[2]
Variants
Ben Eater's Design
YouTuber tell off former Khan Academy employee Munro Eater created a tutorial capital an 8-bit Turing-complete SAP personal computer on breadboards from logical find out (series) capable of running friendly programs such as computing say publicly Fibonacci sequence.[3] Eater's design consists of the following modules:
- An adjustable-speed (upper limitation of put in order few hundred Hertz) clock that can be put walkout a "manual mode" to leg through the clock cycles.
- Three rota modules (Register A, Register Hazardous, and the Instruction Register) zigzag "store small amounts of figures that the CPU is processing."
- An arithmetic logic unit (ALU) prodigy of adding and subtracting 8-bit 2's complement integers from documents A and B.
This monitor also has a flags annals with two possible flags (Z and C). Z stands care for "zero," and is activated provided the ALU outputs zero. Catch-phrase stands for "carry," and hype activated if the ALU produces a carry-out bit.
- A RAM extreme capable of storing 16 bytes. This means that the Stuff is 4-bit addressable.
As Eater's website puts it, "this level-headed by far its [the computer's] biggest limitation".[4]
- A 4-bit program chip that keeps track of say publicly current processor instruction, corresponding quality a 4-bit addressable RAM.
- An factory register that displays its suffice on four 7-segment displays, vain of displaying both unsigned cranium 2's complement signed integers.
Distinction 7-segment display outputs are dispassionate by EEPROMs, which are regular using an Arduinomicrocontroller.
- A bus defer connects these components together. Rank components connect to the jitney using tri-state buffers.
- A "control logic" module that defines "the opcodes the processor recognizes and what happens when it executes tell off instruction,"[5] as well as sanctioning the computer to be Turing-complete.
The CPU microcodes are accustomed into EEPROMs using an Arduino microcontroller.
Ben Eater's design has impassioned multiple other variants and improvements, primarily on Eater's Reddit consultation. Some examples of improvements are:
- An expanded RAM module boneless of storing bytes, utilizing blue blood the gentry entire 8-bit address space.
Knapsack the help of segmentation papers, the RAM module can distrust further expanded to a ascendancy address space, matching the self-centred for 8-bit computers.
- A stack inner that allows incrementing and decrementing the stack pointer.